1. Field of the Invention
This invention relates to a semiconductor memory device and more particularly to the memory cell structure of a static random access memory (SRAM) and the structure of a memory cell array having the memory cells arranged in a matrix form.
2. Description of the Related Art
In recent years, the size of transistors including memory cells is reduced in order to enhance the integration density of a semiconductor memory device. Further, the threshold voltage of the transistor is lowered with a lowering in the power supply voltage. With the reduction in the transistor size and lowering in the threshold voltage, there occurs a problem that variation in the threshold voltages of the transistors configuring the memory cell becomes large. Therefore, in the SRAM, there occurs a problem that a so-called static noise margin (SNM) becomes small due to the influence by variation in the threshold voltages of the transistors configuring the memory cell and memory cells which do not have a sufficiently large SNM are formed.
In the memory cells which do not have a sufficiently large SNM, there occurs a possibility that write disturb and read disturb will occur. That is, when the potential of a certain word line is set to an “H” level in order to write data into a memory cell or read out data from a memory cell, NMOS transfer gates of all of the memory cells connected to the word line are turned ON. At this time, in the memory cell which does not have a sufficiently large SNM and is unstable in the data holding characteristic, there occurs a possibility that the latch state of a latch circuit for data storage will be inverted and stored data will be destroyed.
The technique for stabilizing the data storage state and increasing the cell current to enhance the operation speed is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2005-302231. The memory cell structure used in the technique is attained by adding a transfer gate exclusively used for reading and a read buffer transistor to a 6-transistor SRAM cell. The 6-transistor SRAM cell is used as a data holding section and the transfer gate exclusively used for reading and read buffer transistor are used as a read stage. The threshold voltage of the transistors configuring the data holding section is set higher than the threshold voltage of the transistors configuring the read stage.